1. Field of the Invention
The present invention generally relates to charge loss restoration methods and semiconductor memory devices, and more particularly to a charge loss restoration method for detecting and restoring a charge loss of a memory cell, and to a semiconductor memory device employing such a charge loss restoration method.
2. Description of the Related Art
With respect to a nonvolatile semiconductor memory device such as a flash memory having a structure that stores data by accumulating a charge at a floating gate, an accelerated life test is carried out before the nonvolatile semiconductor memory device is forwarded so to make a screening or a redundancy substitution of memory cells indicating a charge loss. The accelerated life test may be an electric field accelerated life test that applies a high voltage to a word line or a bit line or, a high temperature accelerated life test that applying a high temperature to the nonvolatile semiconductor memory device by baking. In other words, the electric field accelerated life test or the high temperature accelerated life test creates a condition approximating an operation guarantee period of the nonvolatile semiconductor memory device, for example, and the memory cell indicating a charge loss outside a tolerable range is substituted by a redundant memory cell. However, after the nonvolatile semiconductor memory device is forwarded and assembled into a system, it is impossible to remedy the charge loss that occurs in the nonvolatile semiconductor memory device that has been assembled into the system.
FIG. 1 is a diagram showing a relationship of threshold values of a written memory cell and an erased memory cell and a read reference cell in a conventional nonvolatile semiconductor memory device. In FIG. 1, the ordinate indicates a drain-source current Ids of a transistor forming each memory cell in arbitrary units, and the abscissa indicates a gate-source voltage Vgs of the transistor forming each memory cell in arbitrary units. In addition, FIG. 2 is a diagram showing distributions of the written cell and the erased cell in the conventional nonvolatile semiconductor memory device. In FIG. 2, the ordinate indicates a number of memory cells in arbitrary units, and the abscissa indicates a threshold value in arbitrary units. As indicated by an arrow in FIG. 1, the characteristics of the memory cells are such that the written cell makes a transition towards the lower threshold value (charge loss) as the memory cells deteriorate with time.
The applicants are aware of a Japanese Laid-Open Patent Application No. 2002-74999 which proposes a nonvolatile semiconductor memory device having a circuit for detecting the charge loss and the charge gain.
Normally, the write is made with respect to the memory cell to a threshold value that does not result in an erroneous read judgement even when the memory cell deteriorates with time, and no problem occurs in the case of a normal memory cell. In addition, in the case of a memory cell that results in the erroneous read judgement, it is possible to substitute the memory cell by a suitable redundant memory cell prior to forwarding the nonvolatile semiconductor memory device, because the memory cell that results in the erroneous read judgement can be screened by the electric field acceleration test or the high temperature acceleration test. However, there exists a memory cell that cannot be screened by the electric field acceleration test or the high temperature acceleration test, but for some reason exhibits a characteristic abnormality indicated by X1 in FIG. 2 after the nonvolatile semiconductor memory device is forwarded. In the memory cell which exhibits such a characteristic abnormality, the threshold values change to an erroneous read judgement region by moving outside the main distributions of the written cell, and although this memory cell is defective, this defective memory cell cannot be substituted by a redundant memory cell after the nonvolatile semiconductor memory device is forwarded.